Half Subtractor

Description:

A Half Subtractor is a digital circuit that subtracts two single-bit binary numbers. It produces two outputs: the difference and a borrow bit, which indicates if a borrow was needed.

Block Diagram:

<span class="selected">      A  ----|       |---- Difference
             |  HS    |
      B  ----|       |---- Borrow
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Where:

• A is the minuend.
• B is the subtrahend.
• HS represents the Half Subtractor circuit.
• Difference is the result of A – B.
• Borrow indicates if a borrow was needed.

Truth Table:

A	B	Difference	Borrow
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

Verilog Code:

<span class="selected">module half_subtractor(input A, input B, output Difference, output Borrow);
  assign Difference = A ^ B;
  assign Borrow     = (~A) & B;
endmodule
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Test Bench Code:

<span class="selected">module half_subtractor_tb;
  reg A, B;
  wire Difference, Borrow;

  half_subtractor hs_test(
    .A(A),
    .B(B),
    .Difference(Difference),
    .Borrow(Borrow)
  );

  initial begin
    A = 0; B = 0; #10;
    A = 0; B = 1; #10;
    A = 1; B = 0; #10;
    A = 1; B = 1; #10;
    $finish;
  end

  initial begin
    $monitor("A=%b, B=%b, Difference=%b, Borrow=%b", A, B, Difference, Borrow);
  end

endmodule
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