Procedural blocks in SystemVerilog are used to describe the behavior of a digital design at the algorithmic level. They provide a mechanism to specify a sequence of operations that execute over time.

Types of Procedural Blocks:

1. Always Block:

   • Executes continuously, reacting to changes in its sensitivity list.
   • Can be used to model combinational and sequential logic.

   Syntax:

   always @(sensitivity_list) begin
       // Procedural statements
   end
   

   Sensitivity List:

   • Can include signals, clock edges, or level-sensitive events.
   • Common sensitivity lists:
     • @(posedge clk): Positive edge of the clock signal.
     • @(negedge clk): Negative edge of the clock signal.
     • @(*): Sensitivity to any change in any signal in the sensitivity list.
     • @(posedge clk or negedge rst): Positive edge of the clock or negative edge of the reset.

2. Initial Block:

   • Executes only once at the beginning of simulation.
   • Often used for initialization purposes.

   Syntax:

   initial begin
       // Procedural statements
   end
   

Procedural Statements:

• Blocking Assignments (<=): Assign a value to a variable immediately.
• Non-blocking Assignments (=): Schedule an assignment to take effect at the end of the current time step.
• Event Control Statements:
  • #delay: Delay for a specified number of time units.
  • ##delay: Delay for a specified number of delta cycles.
• Conditional Statements: if-else statements.
• Loop Statements: for, while, and forever loops.
• Procedural Continuous Assignments: Assign a value to a variable continuously, similar to a continuous assignment in a module.

Example:

module simple_counter(
    input clk,
    input rst,
    output reg [3:0] count
);

always @(posedge clk, posedge rst) begin
    if (rst)
        count <= 0;
    else
        count <= count + 1;
end

endmodule

Key Points:

• Timing Control: The #delay and ##delay statements are used to control the timing of operations within a procedural block.
• Blocking vs. Non-blocking Assignments: Understanding the difference between blocking and non-blocking assignments is crucial for writing correct and efficient SystemVerilog code.
• Sensitivity Lists: The sensitivity list determines when an always block is triggered.
• Procedural Continuous Assignments: These assignments are useful for modeling combinational logic and driving signals continuously.