SystemVerilog supports two types of arrays:

1. Packed Arrays:

   • Elements are stored in contiguous memory locations.
   • Access individual bits or groups of bits.
   • Commonly used for representing bus signals, register values, and memory addresses.

   Syntax:

   Code snippet

   logic [7:0] byte_array; // 8-bit packed array
   

2. Unpacked Arrays:

   • Elements are stored in separate memory locations.
   • Access individual elements using an index.
   • Commonly used for representing queues, stacks, and other data structures.

   Syntax:

   Code snippet

   int array [10]; // Unpacked array of 10 integers
   

Array Declaration and Initialization:

• Implicit Declaration:

  Code snippet

  logic [7:0] byte_array; // Declares and implicitly initializes to 0
  

• Explicit Declaration and Initialization:

  Code snippet

  int array [3] = '{10, 20, 30}; // Declares and initializes an array
  

Array Access:

• Packed Arrays:

  Code snippet

  logic bit0 = byte_array[0]; // Access the first bit
  logic byte1 = byte_array[7:4]; // Access bits 7 to 4
  

• Unpacked Arrays:

  Code snippet

  int first_element = array[0]; // Access the first element
  int last_element = array[2]; // Access the last element
  

Array Operations:

• Assignment:

  Code snippet

  array[1] = 40; // Assign a value to an array element
  

• Looping:

  Code snippet

  for (int i = 0; i < 3; i++) begin
      array[i] = i * 10;
  end
  

Multidimensional Arrays:

SystemVerilog supports multidimensional arrays:

int matrix [2][3]; // 2D array of integers

Dynamic Arrays:

SystemVerilog allows dynamic arrays, where the size can be determined at runtime:

int dynamic_array[$]; // Dynamic array

// Allocate memory for 10 elements
dynamic_array = new[10];