SystemVerilog Operators

SystemVerilog Operators: A Comprehensive Guide

SystemVerilog provides a rich set of operators for manipulating data and performing various operations. Understanding these operators is crucial for effective hardware design and verification.

1. Arithmetic Operators

Operator Description Example
+ Addition result = a + b;
- Subtraction result = a - b;
* Multiplication result = a * b;
/ Division result = a / b;
% Modulus (remainder) result = a % b;
** Exponentiation result = a ** b;

2. Relational Operators

Operator Description Example
> Greater than if (a > b) ...
< Less than if (a < b) ...
>= Greater than or equal to if (a >= b) ...
<= Less than or equal to if (a <= b) ...
== Equal to if (a == b) ...
!= Not equal to if (a != b) ...

3. Equality Operators

Operator Description Example
=== Case equality (includes X and Z) if (a === b) ...
!== Case inequality (includes X and Z) if (a !== b) ...

4. Logical Operators

Operator Description Example
&& Logical AND if (a && b) ...
` ` Logical OR
! Logical NOT if (!a) ...

5. Bitwise Operators

Operator Description Example
& Bitwise AND result = a & b;
` ` Bitwise OR
^ Bitwise XOR result = a ^ b;
~ Bitwise NOT (inversion) result = ~a;
~& Bitwise NAND result = ~(a & b);
`~ ` Bitwise NOR
~^ Bitwise XNOR result = ~(a ^ b);

6. Shift Operators

Operator Description Example
<< Left shift result = a << 2;
>> Right shift (arithmetic) result = a >> 2;
>>> Right shift (logical) result = a >>> 2;

7. Reduction Operators

Operator Description Example
& Bitwise AND reduction result = &a; // AND of all bits in 'a'
` ` Bitwise OR reduction
^ Bitwise XOR reduction result = ^a; // XOR of all bits in 'a'

8. Concatenation Operator

Operator Description Example
{ } Concatenates operands result = {a, b};

9. Replication Operator

Operator Description Example
{n{data}} Replicates ‘data’ ‘n’ times result = {4{1'b0}}; // 0000

10. Assignment Operators

Operator Description Example
= Simple assignment a = b;
+= Add and assign a += b;
-= Subtract and assign a -= b;
*= Multiply and assign a *= b;
/= Divide and assign a /= b;
%= Modulus and assign a %= b;