SystemVerilog Data Types Examples

module register_access;

  logic [31:0] address;
  logic [31:0] data;
  logic read, write, clk;

  reg [31:0] reg_file [0:15]; // Unpacked array of registers

  always @(posedge clk) begin
    if (write) begin
      reg_file[address[3:0]] <= data; 
    end else if (read) begin
      data <= reg_file[address[3:0]];
    end
  end

endmodule

module traffic_light_controller;

  typedef enum logic [1:0] {RED, YELLOW, GREEN} state_t; 
  state_t current_state, next_state;

  always @(posedge clk) begin
    case (current_state)
      RED: begin
        next_state = YELLOW;
      end
      YELLOW: begin
        next_state = GREEN;
      end
      GREEN: begin
        next_state = RED;
      end
    endcase

    current_state <= next_state;
  end

endmodule

module simple_queue;

  logic clk, rst;
  logic [7:0] data_in;
  logic [7:0] data_out;
  logic wr_en, rd_en;

  typedef struct packed {
    logic [7:0] data;
    logic valid;
  } queue_entry_t;

  queue_entry_t queue [0:7]; 
  integer head, tail; 

  always @(posedge clk) begin
    if (rst) begin
      head <= 0;
      tail <= 0;
      for (int i = 0; i < 8; i++) begin
        queue[i].valid <= 0;
      end
    end else begin
      if (wr_en && !queue[tail].valid) begin
        queue[tail].data <= data_in;
        queue[tail].valid <= 1;
        tail <= (tail + 1) % 8; 
      end
      if (rd_en && queue[head].valid) begin
        data_out <= queue[head].data;
        queue[head].valid <= 0;
        head <= (head + 1) % 8;
      end
    end
  end

endmodule