Assignment Statements

Introduction to Assignment Statements in SystemVerilog

Assignment statements are fundamental in SystemVerilog. They are used to assign values to variables, nets, and other data types. SystemVerilog offers two primary types of assignment statements:

1. Blocking Assignment (=):

• Execution: The assignment happens immediately.
• Order Matters: Assignments are executed sequentially in the order they appear in the code.
• Example:

a = b; 
c = a + <span class="hljs-number">1</span>; 

In this example, b is assigned to a first, and then a+1 is assigned to c.

2. Non-blocking Assignment (<=)

• Execution: The assignment is scheduled to occur at the end of the current time step.
• Order Independent: Multiple non-blocking assignments within the same always block are scheduled concurrently.
• Example:

a <= b; 
c <= a + <span class="hljs-number">1</span>; 

In this example, the value of b is scheduled to be assigned to a at the end of the time step, and the value of a (before the assignment) is used to calculate c.

Key Differences: