Description:
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A Ripple Carry Adder is a digital circuit that adds two multi-bit binary numbers. It consists of a chain of full adders, where the carry-out of each full adder is connected to the carry-in of the next full adder. The carry ripples through the chain of adders.
Block Diagram:
<span class="selected"> A[3] ----| |---- Sum[3]
| FA3 |---- Carry[3]
B[3] ----| |
Carry[2]
A[2] ----| |---- Sum[2]
| FA2 |---- Carry[2]
B[2] ----| |
Carry[1]
A[1] ----| |---- Sum[1]
| FA1 |---- Carry[1]
B[1] ----| |
Carry[0]
A[0] ----| |---- Sum[0]
Cin ----> | FA0 |---- Carry[0] (Cout)
B[0] ----| |
</span><br class="ProseMirror-trailingBreak" />
Where:
- A[3:0] and B[3:0] are the two 4-bit input numbers.
- Cin is the initial carry-in.
- FA0, FA1, FA2, and FA3 are full adders.
- Sum[3:0] is the 4-bit sum.
- Carry[0] to Carry[3] are the carry bits between the full adders.
- Cout is the final carry-out.
Verilog Code (4-bit Ripple Carry Adder):
<span class="selected">module ripple_carry_adder_4bit(
input [3:0] A,
input [3:0] B,
input Cin,
output [3:0] Sum,
output Cout
);
wire C1, C2, C3; // Intermediate carry signals
full_adder FA0(
.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(Sum[0]), .Carry(C1)
);
full_adder FA1(
.A(A[1]), .B(B[1]), .Cin(C1), .Sum(Sum[1]), .Carry(C2)
);
full_adder FA2(
.A(A[2]), .B(B[2]), .Cin(C2), .Sum(Sum[2]), .Carry(C3)
);
full_adder FA3(
.A(A[3]), .B(B[3]), .Cin(C3), .Sum(Sum[3]), .Carry(Cout)
);
endmodule
</span><br class="ProseMirror-trailingBreak" />
Test Bench Code (4-bit Ripple Carry Adder):
<span class="selected">module ripple_carry_adder_4bit_tb;
reg [3:0] A, B;
reg Cin;
wire [3:0] Sum;
wire Cout;
ripple_carry_adder_4bit rca_test(
.A(A), .B(B), .Cin(Cin), .Sum(Sum), .Cout(Cout)
);
initial begin
Cin = 0;
A = 4'b0000; B = 4'b0000; #10;
A = 4'b0001; B = 4'b0010; #10;
A = 4'b0101; B = 4'b0110; #10;
A = 4'b1010; B = 4'b1011; #10;
A = 4'b1111; B = 4'b1111; #10;
Cin = 1;
A = 4'b0000; B = 4'b0000; #10;
A = 4'b0001; B = 4'b0010; #10;
A = 4'b0101; B = 4'b0110; #10;
A = 4'b1010; B = 4'b1011; #10;
A = 4'b1111; B = 4'b1111; #10;
$finish;
end
initial begin
$monitor("Cin=%b, A=%b, B=%b, Sum=%b, Cout=%b", Cin, A, B, Sum, Cout);
end
endmodule</span>