Full Subtractor -

Description:

Your Roadmap

1 Description:
2 Block Diagram:
3 Truth Table:
4 Verilog Code:
5 Test Bench Code:

A Full Subtractor is a digital circuit that subtracts two single-bit binary numbers, and also considers a borrow-in bit from a previous stage. It produces two outputs: the difference and a borrow-out bit.

Block Diagram:

<span class="selected">         Bin
          |
      A  ----|         |---- Difference
             |  FS     |
      B  ----|         |---- Borrow
</span><br class="ProseMirror-trailingBreak" />

Where:

A is the minuend.
B is the subtrahend.
Bin is the borrow-in bit from the previous stage.
FS represents the Full Subtractor circuit.
Difference is the result of A – B – Bin.
Borrow is the borrow-out bit.

Truth Table:

Bin	A	B	Difference	Borrow
0	0	0	0	0
0	0	1	1	1
0	1	0	1	0
0	1	1	0	0
1	0	0	1	1
1	0	1	0	1
1	1	0	0	0
1	1	1	1	1

Verilog Code:

<span class="selected">module full_subtractor(input A, input B, input Bin, output Difference, output Borrow);
  assign Difference = A ^ B ^ Bin;
  assign Borrow     = ((~A) & B) | ((~A) & Bin) | (B & Bin);
endmodule
</span><br class="ProseMirror-trailingBreak" />

Test Bench Code:

<span class="selected">module full_subtractor_tb;
  reg A, B, Bin;
  wire Difference, Borrow;

  full_subtractor fs_test(
    .A(A),
    .B(B),
    .Bin(Bin),
    .Difference(Difference),
    .Borrow(Borrow)
  );

  initial begin
    A = 0; B = 0; Bin = 0; #10;
    A = 0; B = 0; Bin = 1; #10;
    A = 0; B = 1; Bin = 0; #10;
    A = 0; B = 1; Bin = 1; #10;
    A = 1; B = 0; Bin = 0; #10;
    A = 1; B = 0; Bin = 1; #10;
    A = 1; B = 1; Bin = 0; #10;
    A = 1; B = 1; Bin = 1; #10;
    $finish;
  end

  initial begin
    $monitor("A=%b, B=%b, Bin=%b, Difference=%b, Borrow=%b", A, B, Bin, Difference, Borrow);
  end

endmodule</span>