Half Adder: The Basic Building Block of Addition -

A Half Adder is a fundamental digital circuit that performs the addition of two single-bit binary numbers. It produces two outputs: the sum of the two bits, and a carry bit, which indicates if there is an overflow to the next higher bit.

Block Diagram:

Your Roadmap

1 Block Diagram:
2 Truth Table:
3 Verilog Code:
4 Test Bench Code:

<span class="selected">      A  ----|       |---- Sum
             |  HA   |
      B  ----|       |---- Carry
</span><br class="ProseMirror-trailingBreak" />

Where:

A and B are the input bits.
HA represents the Half Adder circuit.
Sum is the sum of A and B.
Carry is the carry-out bit.

Truth Table:

A	B	Sum	Carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Verilog Code:

<span class="selected">module half_adder(input A, input B, output Sum, output Carry);
  assign Sum = A ^ B; // XOR operation for sum
  assign Carry = A & B; // AND operation for carry
endmodule
</span>

Test Bench Code:

<span class="selected">module half_adder_tb;
  reg A, B;       // Declare inputs as registers
  wire Sum, Carry; // Declare outputs as wires

  // Instantiate the half adder module
  half_adder ha_test(
    .A(A),
    .B(B),
    .Sum(Sum),
    .Carry(Carry)
  );

  // Define the test sequence
  initial begin
    A = 0; B = 0; #10;  // #10 means wait 10 time units
    A = 0; B = 1; #10;
    A = 1; B = 0; #10;
    A = 1; B = 1; #10;
    $finish;         // End the simulation
  end

  //optional display
  initial begin
    $monitor("A=%b, B=%b, Sum=%b, Carry=%b", A, B, Sum, Carry);
  end

endmodule
</span>