Assignment Statements

Introduction to Assignment Statements in SystemVerilog

Assignment statements are a core part of SystemVerilog, used to update variables, nets, and signals during simulation and synthesis. Choosing the correct type of assignment is critical, as it directly impacts how hardware behavior is modeled.

SystemVerilog provides two primary types of assignment statements:

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1. Blocking Assignment (=)

Execution:

The assignment happens immediately, just like in standard programming languages.

Behavior:

Statements execute sequentially in the order they are written. Each statement must complete before the next one begins.

Example:

a = b;
c = a + 1;

Explanation:

• First, b is assigned to a

• Then, the updated value of a is used to compute c

Typical Usage:

• Combinational logic

• Temporary variables inside procedural blocks

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2. Non-blocking Assignment (<=)

Execution:

Assignments are scheduled and take effect at the end of the current time step.

Behavior:

All non-blocking assignments in the same time step execute concurrently, regardless of their order in code.

Example:

a <= b;
c <= a + 1;

Explanation:

• a gets the value of b at the end of the time step

• c is computed using the previous value of a, not the updated one

Typical Usage:

• Sequential logic (flip-flops, registers)

• Clocked always blocks

Key Differences: