SystemVerilog Assertions

SystemVerilog Assertions (SVA) is a powerful language feature used to formally verify the functional correctness of digital designs. It allows you to specify properties that the design must satisfy, and then automatically check these properties during simulation or formal verification.

Key Concepts of SVA:

  • Assertion Statements: These statements define the properties that the design must satisfy.
  • Sequence Expressions: Sequence expressions represent a sequence of events that must occur in a specific order.
  • Property Specifications: These specify the temporal relationships between events and sequences.
  • Immediate Assertions: Check properties at the current simulation time step.
  • Concurrent Assertions: Check properties over multiple clock cycles.

Types of Assertions:

  • Immediate Assertions: 
    assert property (a && b) ##1 c;
  • Concurrent Assertions: 
    always_assert property (a |-> ##2 b);

Common SVA Constructs:

  • Implication (|->): Specifies that if one event occurs, another event must follow.
  • Sequence Concatenation (##): Concatenates sequences in time.
  • Logical Operators (&&, ||, !): Combine sequences and properties logically.
  • Temporal Operators (##, throughout, always): Define temporal relationships between events.
  • Quantifiers (forall, some): Specify conditions that must hold for all or some elements of a set.

Benefits of Using SVA:

  • Early Bug Detection: Identify design errors early in the design cycle.
  • Improved Design Quality: Ensure that the design meets functional specifications.
  • Increased Design Confidence: Rigorous verification provides confidence in the design’s correctness.
  • Reduced Verification Effort: Automate the verification process and reduce manual effort.

Advanced SVA Techniques:

  • Cover Property: Checks if a certain sequence of events occurs.
  • Assume Property: Assumes that a certain property holds true.
  • Restrict Property: Restricts the set of possible input sequences.
  • Disable iff Property: Disables an assertion under certain conditions.

Example of an SVA Assertion:

always_assert property (
  @(posedge clk)
  disable iff (reset)
  (req |-> ##2 ack)
);

This assertion checks that if a request (req) is asserted, an acknowledgment (ack) must be asserted two clock cycles later, unless the reset signal is active.

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